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MC100EP40 3.3V / 5V ECL Differential Phase-Frequency Detector
The MC100EP40 is a three-state phase-frequency detector intended for phase-locked loop applications which require a minimum amount of phase and frequency difference at lock. Advanced design significantly reduces the dead zone of the detector. For proper operation, the input edge rate of the R and V inputs should be less than 5 ns. The device is designed to work with a 3.3 V / 5 V power supply. When Reference (R) and Feedback (FB) inputs are unequal in frequency and/or phase the differential UP (U) and DOWN (D) outputs will provide pulse streams which when subtracted and integrated provide an error voltage for control of a VCO. When Reference (R) and Feedback (FB) inputs are 80 ps or less in phase difference, the Phase Lock Detect pin will indicate lock by a high state (VOH). The VTX (VTR, VTR, VTFB, VTFB) pins offer an internal termination network for 50 W line impedance environment shown in Figure 2. An external sinking supply of VCC-2 V is required on VTX pin(s). If you short the two differential VTR and VTR (or VTFB and VTFB) together, you provide a 100 W termination resistance that is compatible with LVDS signal receiver termination. For more information on termination of logic devices, see AND8020. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. For more information on Phase Lock Loop operation, refer to AND8040. Special considerations are required for differential inputs under No Signal conditions to prevent instability.
http://onsemi.com MARKING DIAGRAM
20 20 1 TSSOP-20 DT SUFFIX CASE 948E A L Y W 100 EP40 ALYW 1
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC100EP40DT Package TSSOP-20 Shipping 75 Units/Rail
MC100EP40DTR2 TSSOP-20 2500 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
* * * * * * * * *
Maximum Frequency > 2 GHz Typical Fully Differential Advanced High Band Output Swing of 400 mV Theoretical Gain = 1.11 Trise 97 ps Typical, Ffall 70 ps Typical The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V 50 W Internal Termination Resistor
(c) Semiconductor Components Industries, LLC, 2004
1
January, 2004 - Rev. 8
Publication Order Number: MC100EP40/D
MC100EP40
VCC PLD 20 19 VCC 18 D 17 D 16 U 15 U 14 VCC 13 NC 12 VEE 11
PIN DESCRIPTION
PIN U, U D, D FB, FB R, R FUNCTION ECL Up Differential Outputs ECL Down Differential Outputs ECL Feedback Differential Inputs ECL Reference Differential Inputs ECL Phase Lock Detect Function ECL Internal Termination for R ECL Internal Termination for R ECL Internal Termination for FB ECL Internal Termination for FB Reference Voltage Output Positive Supply Negative Supply No Connect
1
2
3
4
5 FB
6 R
7 R
8
9
10
PLD VTR VTR VTFB VTFB VBB VCC VEE NC
VEE VTFB VTFB FB
VTR VTR VBB
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View)
VTR 50 W R R 50 W VTR U A A S Reset FF R C D B VTFB Reset 50 W (V) FB FB 50 W VTFB VBB D B B D R FF S B D Reset D D D Reset U A C C A U U
Figure 2. Logic Diagram ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value N/A N/A > 4 kV > 400 V > 2 kV Level 1 UL 94 V-0 @ 0.125 in 699 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
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MC100EP40
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 20 TSSOP 20 TSSOP 20 TSSOP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 140 100 23 to 41 265 Units V V V V mA mA mA C C C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) PLD Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 5) Input HIGH Current Input LOW Current -150 U, U, B, B Min 100 2225 1775 1355 2075 1355 1775 2.0 1875 Typ 128 2350 1900 1480 Max 160 2475 2025 1605 2420 1675 1975 3.3 150 -150 Min 100 2275 1800 1355 2075 1355 1775 2.0 1875 25C Typ 130 2400 1925 1480 Max 160 2525 2050 1605 2420 1675 1975 3.3 150 -150 Min 110 2300 1825 1355 2075 1355 1775 2.0 1875 85C Typ 140 2425 1950 1480 Max 170 2550 2075 1605 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 W to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100EP40
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL Characteristic Power Supply Current (Note 7) Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 9) Input HIGH Current Input LOW Current -150 U, U, B, B PLD Min 100 3925 3475 3055 3775 3055 3475 2.0 3575 Typ 128 4050 3600 3180 Max 160 4175 3725 3305 4120 3375 3675 5.0 150 -150 Min 100 3975 3500 3055 3775 3055 3475 2.0 3575 25C Typ 130 4100 3625 3180 Max 160 4225 3750 3305 4120 3375 3675 5.0 150 -150 Min 110 4000 3525 3055 3775 3055 3475 2.0 3575 85C Typ 140 4125 3650 3180 Max 170 4250 3775 3305 4120 3375 3675 5.0 150 Unit mA mV mV mV mV mV V mA mA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 7. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 8. All loading with 50 W to VCC-2.0 volts. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 10)
-40C Symbol IEE VOH VOL Characteristic Power Supply Current (Note 11) Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) U, U, B, B PLD Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 13) Input HIGH Current Input LOW Current -150 Min 100 -1075 -1525 -1945 -1225 -1945 -1525 -1425 Typ 128 -950 -1400 -1820 Max 160 -825 -1275 -1695 -880 -1625 -1325 0.0 150 -150 Min 100 -1025 -1500 -1945 -1225 -1945 -1525 -1425 25C Typ 130 -900 -1375 -1820 Max 160 -775 -1250 -1945 -880 -1625 -1325 0.0 150 -150 Min 110 -1000 -1475 -1945 -1225 -1945 -1525 -1425 85C Typ 140 -875 -1350 -1820 Max 170 -750 -1225 -1945 -880 -1625 -1325 0.0 150 mV mV mV V mA mA Unit mA mV mV
VIH VIL VBB VIHCMR IIH IIL
VEE+2.0
VEE+2.0
VEE+2.0
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 10. Input and output parameters vary 1:1 with VCC. 11. For (VCC - VEE) >3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC-VEE operation at 3.3 V. 12. All loading with 50 W to VCC-2.0 volts. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100EP40
AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 14)
-40C Symbol fmax tPLH, tPHL tJITTER VPP tr tf Characteristic Maximum Frequency (See Figure 3. Fmax/JITTER) Propagation Delay to Output Differential Random Clock Jitter (See Figure 3. Fmax/JITTER) Input Voltage Swing (Differential) Output Rise/Fall Times (20% - 80%) Q, Q 150 60 FB to D/U R to D/U 400 Min Typ >2 525 0.2 800 85 700 <1 1200 130 150 60 410 Max Min 25C Typ >2 550 0.2 800 110 750 <1 1200 150 150 80 450 Max Min 85C Typ >2 575 0.2 800 120 775 <1 1200 160 Max Unit GHz ps ps mV ps
14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V.
550 VOUTamplitude (mVpp) 500 5V 450 3.3 V 400 350 300
10 9 8 7 6 5 4 3 2 1 JITTEROUT ps (RMS)
250 1.0
Driver Device Q 50 W 50 W D
Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
IIIIIIIIIIIIIIII II II
(JITTER) 0 1.5 2.0 FREQUENCY (GHz) 2.5
Figure 3. Fmax/Jitter @ 255C
Q
D Receiver Device
V TT V TT = V CC - 2.0 V
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MC100EP40
Resource Reference of Application Notes
AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020 - - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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MC100EP40
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
B L
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N M DETAIL E
2X
L/2
20
11
K K1
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
MC100EP40
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MC100EP40/D

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